System Validation Engineer (New Grads)

Responsibilities

• • Perform root-cause and failure analysis across RISC-V hardware and software components.
• • Use ILA and JTAG debugging tools to investigate FPGA designs.
• • Develop systematic hypotheses to identify the causes of failures.
• • Create and maintain Python scripts for debugging and automation.
• • Support validation activities for RISC-V CPUs.
• • Work with FPGA-based platforms and development boards.
• • Gain practical exposure to RISC-V processors and its software ecosystem.

Requirements

• • Bachelor's or Master's degree in Computer Science or Electronics and Communication Engineering.
• • Strong knowledge of computer architecture.
• • Understanding of logic design.
• • Experience with Verilog.
• • Experience working with FPGA platforms.
• • Practical Linux experience.
• • Python and BASH scripting knowledge.
• • Strong analytical and debugging abilities.
• • Positive attitude and willingness to continuously learn.

Skills

Eligibility

• • Bachelor's or Master's degree in Computer Science or Electronics and Communication Engineering.
• • Strong understanding of computer architecture and logic design.
• • Prior exposure to logic design using Verilog.
• • Experience porting designs onto FPGA platforms.
• • Practical experience with Linux-based operating systems.
• • Knowledge of scripting using Python and BASH.
• • The role is specifically identified as a New Grads position.
• • Candidates should demonstrate a proactive approach to learning.
• • Graduation year: 2025,2026.
• • Successful background and reference checks are required.
• • Work authorization requirements apply based on the selected location.